Wafer Bumping & UBM
Complete under-bump metallization and bump formation — solder bumps, Cu pillars, Au studs, and micro-bumps. From single-die assembly to 3D chip stacking at pitches down to 10μm.
Overview
Wafer bumping is the critical interconnect technology that bridges the gap between fabricated ICs and their packaging substrate — converting planar Al or Cu bond pads into three-dimensional solder, copper, or gold interconnects ready for flip-chip assembly, wafer-level packaging, or 3D stacking.
GINECHIP provides a complete wafer bumping service encompassing the full process flow: surface preparation and passivation repassivation, UBM deposition (sputtered or electroless), photolithographic patterning for bump definition, electroplating or stud bonding for bump formation, and reflow/singulation for finished bumped wafers. Every lot includes UBM thickness mapping, bump height coplanarity measurement, and shear strength testing.
Bump Technologies
Solder Bumps (C4 — Controlled Collapse Chip Connection)
Reflowable solder spheres or electroplated pillars that form the primary interconnect between die and substrate. Industry-standard solder alloys optimized for specific reflow profiles, reliability requirements, and environmental compliance (RoHS). Applications from flip-chip BGA to 2.5D interposer attachment.
Cu Pillar Bumps
High-aspect-ratio copper columns capped with a solder layer. Cu pillars offer superior electromigration resistance, better thermal conductivity, and finer pitch capability compared to traditional solder bumps. The dominant interconnect for advanced nodes (sub-28nm) and high-density fan-out packaging.
Au Stud Bumps
Thermosonic wire-bonded gold studs that are flattened to form planar interconnects. Fluxless bonding process — ideal for optoelectronic devices (VCSELs, photodetectors), MEMS hermetic sealing, and applications where solder flux contamination is unacceptable.
Micro-Bumps (μ-Bump)
Ultra-fine-pitch interconnects for 3D-IC stacking, HBM (High Bandwidth Memory) integration, and die-to-wafer hybrid bonding. Typical pitches of 10–55μm with Cu/Sn or Cu/Ni/Sn metallurgy. Essential for chiplet architectures and heterogeneous integration platforms.
Under-Bump Metallization (UBM) Stacks
The UBM is the multi-layer thin-film stack that provides adhesion to the IC bond pad, a diffusion barrier against intermetallic formation, and a wetting layer for solder reflow. The right UBM selection is critical for reliability — governing electromigration lifetime, thermal cycling resistance, and intermetallic compound (IMC) growth kinetics.
Ti/Cu
Titanium adhesion/diffusion barrier + copper seed layer. The workhorse UBM for SAC and SnAg solder bumps on Al pads. Sputtered or evaporated. TiW variant for higher thermal budget.
TiW/Cu
TiW (10 wt% Ti) offers superior diffusion barrier properties at elevated temperatures versus pure Ti. Preferred for high-power RF devices and automotive-grade reliability requirements.
Cr/CrCu/Cu
Chromium-based adhesion with graded CrCu interlayer to manage film stress. Excellent adhesion to dielectrics and common in older-generation bumping technologies.
Ni/Au (ENIG/ENEPIG)
Electroless Ni (3–5μm) with immersion Au (0.05–0.15μm). ENEPIG variant adds electroless Pd for wire-bonding compatibility. Low-cost, maskless UBM process.
Al/NiV/Cu
Aluminum pad metallization with sputtered NiV barrier and Cu seed. Common in high-volume flip-chip production. NiV prevents Sn-Ni intermetallic embrittlement.
Ti/Ni/Ag
Low-cost alternative to Au-based stacks. Ti adhesion layer, Ni diffusion barrier, Ag wetting layer. Suitable for Sn-based solders in consumer electronics packaging.
Process Flow
Surface Prep
Plasma clean, wet chemical activation of Al pads. Polyimide or BCB repassivation if required. Removal of native Al₂O₃ for low-contact-resistance UBM adhesion.
UBM Deposition
PVD sputtering or electroless deposition of the full UBM stack — adhesion layer, diffusion barrier, and seed/wetting layer. Thickness uniformity < 3% (1σ).
Bump Patterning
Thick photoresist coating and lithography to define bump locations. Aspect ratio, sidewall profile, and CD optimized for bump type and pitch.
Bump Formation
Electroplating (solder, Cu pillar) or thermosonic stud bonding (Au). In-situ thickness monitoring. Post-plate resist strip and UBM etch.
Reflow & Inspect
Controlled atmosphere reflow (N₂, forming gas) for solder ball formation. Automated optical inspection (AOI), bump height coplanarity, and shear strength testing.
Typical Applications
Direct attach of ICs to organic substrates, ceramic packages, or silicon interposers via C4 solder bumps. Enables highest I/O density and shortest interconnect path for high-speed digital and RF devices.
Au stud bumps or SnAg rings for wafer-level hermetic cavity sealing of accelerometers, gyroscopes, pressure sensors, and RF-MEMS switches.
Au stud bumps for fluxless bonding of GaN LEDs and GaAs VCSEL arrays onto silicon driver ICs or submounts. Eliminates flux residue on optically sensitive surfaces.
Micro-bumps and Cu pillars for die-to-interposer and die-to-die stacking in high-bandwidth memory (HBM), chiplet architectures, and heterogeneous SoC integration.
Solder ball placement on redistribution layer (RDL) pads for wafer-level chip scale packages (WLCSP). Typical ball diameters 200–400μm at 400–800μm pitch.
Reliability & Qualification
Bumped wafers are qualified through a suite of reliability tests aligned with JEDEC standards: shear strength testing (JESD22-B117) for mechanical integrity, thermal cycling (−55°C to +125°C, 1000 cycles) for solder joint reliability, high-temperature storage (150°C, 1000 hrs) for IMC growth characterization, and electromigration testing for current-carrying capability. Dedicated test structures (daisy chains, Kelvin structures) are available for in-situ reliability monitoring.
Quality Assurance
100% automated optical inspection (AOI) post-bump, statistical sampling for bump height coplanarity (laser profilometry, ±2μm target), UBM sheet resistance monitoring, and cross-sectional SEM on monitor die for IMC layer thickness verification. Each lot ships with a full Certificate of Conformance including bump height distribution, shear strength data, and process traceability.
Ready to Start Bumping?
Specify your bump type, UBM stack, pitch, and wafer quantity — our advanced packaging team will provide a detailed technical proposal and quotation within 24 hours.