MEMS Process Services
End-to-end wafer fabrication and processing — from thin-film deposition to final dicing. Reduce multi-vendor complexity with a single, ISO-certified process partner.
Overview
Managing a MEMS or semiconductor fabrication flow across multiple vendors introduces significant complexity: process qualification at each supplier, wafer logistics and shipping delays, interface compatibility risks between process steps, and inconsistent quality documentation. GINECHIP's integrated process services model collapses this multi-vendor supply chain into a single, seamless workflow.
Our eight core process modules — thin-film deposition, photolithography, DRIE etching, wafer bonding, wafer bumping, wafer reclaim, wet/vapor etching, and CMP — are operated under one quality management system in ISO Class 5 cleanroom conditions. This enables reduced cycle time (no inter-vendor shipping), single-source accountability (one Certificate of Conformance covering the entire process flow), and optimized process integration (our engineers ensure each step is compatible with downstream requirements).
Process Modules
Thin-Film Deposition
Complete thin-film deposition services for MEMS and semiconductor wafers. PVD sputtering (DC, RF, magnetron, reactive), e-beam and thermal evaporation, PECVD, LPCVD, ALD, and electroplating. Metals (Al, Ti, Au, Pt, Cu, Cr, Ni), dielectrics (SiO₂, Si₃N₄, Al₂O₃, HfO₂), semiconductors (poly-Si, a-Si), and polymers (polyimide, BCB, parylene).
Photolithography
Precision wafer patterning using five distinct exposure technologies. Contact and proximity lithography (0.5–5μm), i-line projection stepper (0.35μm), maskless laser direct write (0.6μm), and nanoimprint lithography (< 50nm). Full resist processing including coat, soft/hard bake, develop, and descum. Double-side alignment capability.
DRIE — Deep Reactive Ion Etching
High-aspect-ratio silicon etching via Bosch process (SF₆/C₄F₈交替 cycles) for MEMS structures. Aspect ratios exceeding 30:1 with vertical sidewall profiles (89° ± 0.5°). Through-wafer etching for TSVs and membrane release. Cryogenic and non-Bosch processes available for smooth sidewall applications.
Wafer Bonding
Permanent and temporary wafer bonding technologies for MEMS encapsulation and 3D stacking. Anodic bonding (Si-glass, 300–500°C), fusion bonding (Si-Si, Si-SiO₂, high-temp anneal), eutectic bonding (Au-Si 363°C, AuSn 280°C), adhesive bonding (BCB, SU-8, epoxy). Wafer-level hermetic sealing for vacuum-packaged devices.
Wafer Bumping & UBM
Wafer-level interconnect formation for flip-chip and 3D stacking. Solder bumps (SnAg, SAC, AuSn), Cu pillars (20–80μm pitch), Au stud bumps (fluxless, clean process), and micro-bumps (10–55μm pitch). Full UBM metallization stacks: Ti/Cu, TiW/Cu, Cr/CrCu/Cu, electroless Ni/Au.
Wafer Reclaim & Reprocessing
Restore used test and monitor wafers to virgin-grade surface quality. Selective chemical stripping of films (oxide, nitride, metal, resist), CMP re-polishing to Ra < 0.5nm, and full metrology re-certification. Silicon, SOI, glass, and GaAs substrates up to 300mm. Reduce wafer procurement costs by up to 70%.
Wet & Vapor Etching
Isotropic and anisotropic chemical etching for MEMS structure release and surface preparation. KOH (anisotropic Si, 〈111〉 etch stop), TMAH (CMOS-compatible), BOE/HF (oxide etch and sacrificial release), H₃PO₄ (nitride strip). HF vapor etching for stiction-free sacrificial oxide release of suspended microstructures. Critical point drying (CPD) available.
CMP — Chemical Mechanical Polishing
Planarization and surface finishing for multi-level MEMS structures. Oxide CMP (ILD planarization), tungsten CMP (via plugs), copper CMP (damascene RDL), and silicon CMP (surface preparation). Sub-nanometer RMS surface finish with tight within-wafer uniformity (< 2% 1σ).
Fab Capabilities at a Glance
| Capability Area | Details |
|---|---|
| Cleanroom Class | ISO Class 5 (Class 100) for lithography; ISO Class 6 (Class 1,000) for wet processing and CMP |
| Wafer Sizes | Fragments, 100mm (4″), 150mm (6″), 200mm (8″), 300mm (12″). Multi-size cassette compatibility. |
| Substrate Materials | Silicon (CZ, FZ, all grades), SOI, glass (fused silica, borosilicate, quartz), GaAs, InP, SiC, sapphire, ceramics |
| Metrology Suite | SEM, AFM, spectroscopic ellipsometry, 4-point probe, optical profilometry, laser surface scanner, XRD, contact angle goniometer |
| Data Formats | GDSII, OASIS, DXF, CIF for lithography. Standardized process travelers with full lot traceability. |
| Process Control | SPC (statistical process control) on critical parameters. Run-to-run thickness and CD control. Monthly process capability reports. |
| Certifications | ISO 9001:2015 certified quality management. SEMI Standards compliance. ITAR registered for defense-related work. |
| Volume Capability | Single-wafer R&D up to pilot production volumes (hundreds of wafers/month). Flexible scheduling for academic and startup timelines. |
End-to-End Process Integration
What differentiates GINECHIP from single-process vendors is our ability to manage multi-step, multi-module process flows as an integrated service. A typical MEMS accelerometer fabrication flow — for example — might include: substrate preparation (Si or SOI wafer supply) → PVD electrode deposition (Ti/Au) → photolithography (comb-drive patterning) → DRIE (silicon etch for proof mass release) → wet etch (sacrificial oxide removal + CPD) → wafer bonding (hermetic cap seal with TSV feedthrough) → wafer-level electrical test → dicing.
Instead of managing five different vendors across three countries, our customers receive a single project plan, a single process traveler, and a single Certificate of Conformance. Our process engineers act as your virtual fab integration team — anticipating interface issues, optimizing process parameters holistically, and delivering finished devices ready for packaging and test.
Custom Process Development
Not every process step is off-the-shelf. For customers developing novel MEMS devices with unique material stacks, non-standard geometries, or emerging process requirements, we offer custom process development services. This includes: design-of-experiments (DOE) to optimize individual process parameters, split-lot processing for A/B comparison, process window characterization (center-point and edge-of-window verification), and full process documentation for technology transfer to volume manufacturing.
From Prototype to Production
Our process services are designed to scale with you. Start with single-wafer engineering runs for feasibility demonstration and design validation. Move to small-batch prototyping (5–25 wafers) for yield optimization and reliability testing. Transition to pilot production (50–200 wafers/month) with SPC-controlled processes and established baseline yields. Throughout this journey, process parameters and quality specifications remain consistent — eliminating the costly re-qualification that often accompanies vendor transitions between development and production phases.
Ready to Streamline Your Process Flow?
Share your process sequence, wafer specifications, and target volume — our engineering team will design an integrated process plan and provide a comprehensive quotation within 24 hours.